There has been a growing interest in developing electronic devices using metal oxides as the semiconductor component. These devices can offer advantages such as structural flexibility (e.g., foldability or bendability), potentially much lower manufacturing costs, and the possibility of low-temperature ambient manufacturing processes on large areas. Particularly, metal oxide semiconductors such as indium gallium zinc oxide (IGZO) can exhibit high charge carrier mobility and be processed at temperatures far lower than those required for silicon. Thus, metal oxide semiconductors can be used to enable new devices such as electronic paper, rigid or flexible organic light-emitting diode (OLED) displays, ultra-high resolution displays, radio-frequency identification (RFID) technologies, and transparent displays and circuits.
One of the key benefits to using metal oxides is the potential to use both vapor-phase and solution-phase deposition techniques to deposit the semiconductor as well as other materials needed to fabricate these devices. Yet, to further realize the processing advantages of metal oxide semiconductors, all active components of the device should be mechanically flexible and, preferably, most of the components of the device should be compatible with, if not processable by, solution-phase deposition fabrication.
For example, thin-film transistors (TFTs) based upon various solution-processed or vapor-deposited metal oxide semiconductors have been developed. However, critical components in TFTs are the layers in the proximity of the oxide semiconductor channel layers, which include the gate dielectric layer, the etch-stop, and/or the passivation layer, depending on the TFT device architecture (see FIG. 1).
As far as the gate dielectric layer is concerned, it comprises an electrically insulating material that enables the creation of the gate field between the source electrode and the gate electrode. Thus, the gate dielectric layer functions to prevent leakage currents from flowing from the channel to the gate electrode when a voltage is applied to the gate. In addition to exhibiting low-gate leakage properties, a good dielectric material also needs to be air- and moisture-stable, and should be robust enough to withstand common device fabrication process conditions, with properties that are tunable depending on the type of semiconductor employed in the TFT channel. Particularly, for vapor-deposited metal oxide semiconductor-based TFTs, the dielectric material must be able to withstand sputtering conditions and thermal annealing of the semiconductor, a process typically requiring relatively high temperatures (˜250-300° C.).
Regarding the other layers in contact with the channel, in the case of an etch-stop (ES) transistor structure, the material used for the etch stop layer, first and foremost, must be able to prevent damage of the oxide channel when the source/drain electrical contacts are defined via photolitography. The ES material must exhibit strong adherence to the metal oxide layer, and should be able to withstand conditions required to thermally anneal the oxide layer, without compromising the charge transport property of the oxide channel layer. Furthermore, in the ES architecture, a second layer acting as a passivation layer typically is deposited on top of the metal oxide/electrode surface. Therefore, the ES layer, in addition to showing strong adherence to the oxide channel layer, also must adhere strongly to the passivation layer. Furthermore, the ES layer should act as a moisture barrier for the oxide channel layer while planarizing its surface. The ES material also must be able to sustain device processing conditions that take place on top of it. In an alternative transistor architecture known as back-channel-etch (BCE) structure, the oxide semiconductor is placed in direct contact with the passivation layer. This passivation layer should have properties similar to those used in the ES architecture although the BCE structure requires adhesion of the passivation material directly to the oxide layer and not to the ES layer.
Although some polymers have been employed as dielectrics for metal oxide TFTs, several limitations of current-generation polymeric dielectric have yet to be overcome. For example, very few polymeric dielectric materials are sufficiently soluble to be solution-processed, especially via inexpensive printing techniques. Among those that are solution-processable, they often cannot survive the conditions used in subsequent processing steps, which significantly limits their application in device fabrication. For TFT device fabrication, the deposition of overlying layers such as the semiconductor layer, the conductor layer(s), and other passive layers by solution-phase processes may require solvents, temperatures, or deposition conditions that compromise the integrity of the dielectric materials. Similarly, most known solution-processable dielectric materials cannot survive vapor-phase deposition methods (e.g., sputtering), which are commonly used to process metals and metal oxides. In addition, currently available polymeric dielectric materials often fail to achieve high surface smoothness, which is a prerequisite for stable TFT performance and operation.
With respect to passivation materials, a few polymeric materials have been envisioned to be used as both the ES layer and the passivation layer. However, it has remained a challenge to identify materials that show excellent thermal stability, photopatternability, and good adhesion to both inorganic (e.g, metals, metal alloys, and metal oxides) and organic materials, while conferring chemical protection to the oxide channel layer. Particularly, conventional photoresists, while providing excellent photopatternability, fail to enable the other requirements.
Accordingly, there is a desire in the art to identify appropriate organic materials and/or design and synthesize new organic materials that are compatible with diverse substrates, conductors, and/or semiconductors such that they could be employed in the whole metal oxide TFT fabrication process to meet one or more device requirements including photopatternability, low current leakage densities, high thermal stability, resistance to harsh chemicals used in patterning steps, tuned surface energies, good adhesion, good solution-processability, and/or low permeation to water.